The advance in VLSI technology has led to the emergence of Systems on Chips (SoC), where a large number of intellectual property cores are integrated onto a single chip. Systems on chip are of high computing performance and how components communicate is the key issue in these systems. The bus–based approach used in traditional systems represents a bandwidth bottleneck in SoC in addition to the non–scalability problem. Therefore light weight networks, known as Network on Chip (NoC), have emerged. NoCs as a promising alternative to the bus–based approach. They have their roots form data communication networks and inherit all issues faced in data communication networks with an extra challenge which is space limitation. As a result, new challenges and issues on the design and implementation of these networks have attracted the attention of several researchers.<br>The workshop on the Design and Performance of Networks on Chip (DPNoC′2014) will represent an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in networks on chip.<br>The Workshop topics include (but are not limited to) the following:<br>Technology constraints on NoCs<br>System and Micro Architecture for NoCs<br>Technology constraints on NoCs<br>System and Micro Architecture for NoCs<br>Flow control<br>Switching techniques<br>Routing protocols<br>Network modeling and performance evaluation<br>Schedling and Application mapping onto NoC<br>NOC scalability<br>Fault tolerance/reliability in NoC<br>Wireless NoC<br>NoCs Applications and Design<br>Multi–Core Systems<br>Floorplanning, Scheduling, and IP Mapping<br>FPGA–based implementation of reconfigurable NoCs<br>Wireless Network–on–Chip<br>
Abbrevation
DPNoC
City
Niagara Falls
Country
Canada
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