Design and Verification Conference and Exhibition Europe, Munich, Deutschland

Abbrevation

DVCon Europe

Link

http://dvcon-europe.org/conf/call/

City

Munich

Country

Germany

Deadline Paper

2014-05-15

Start Date

2014-10-14

End Date

2014-10-15

Abstract

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design. The focus of this highly technical conference is on the practical usage of specialized design and verification languages such as SystemC, SystemVerilog and e; assertions in SVA or PSL; the use of AMS languages; design automation using IP–XACT; and the use of general purpose languages C and C++. Low power techniques are pervasive and can be addressed in the four topics areas below. This call for abstracts solicits presentations that are highly technical and reflect real life experiences in using languages, standards, methods and Electronic Design Automation (EDA) tools. Submissions are encouraged in (but not restricted to) the following areas: Topic area 1: System–level design Transaction–level modeling for system–level design Hardware/software/embedded co–design System–on–chip and network–on–chip design System–level design techniques, flows and methodologies High–level synthesis from ESL languages Virtual and hardware–assisted prototyping Topic area 3: IP reuse and design automation Tool and flow automation using IP–XACT SoC and IP integration methods and tools IP protection and security Configuration management of IP and abstraction levels Interoperability of models and/or tools Topic area 2: Verification & Validation Formal and semi–formal techniques Hardware/software co–verification Using multiple HDLs and/or HVLs in a design cycle Automated stimulus generation methods Advanced methodologies and testbenches in UVM Verification process and resource management Requirements–driven verification Topic area 4: Mixed–signal design and verification Mixed–signal design and verification techniques Real–value modeling approaches Application of mixed–signal extensions for UVM AMS sytem–level and concept design Self–checking of analog simulation