6th Workshop on Design for 3D Silicon Integration, Lausanne, Schweiz

3&#8211;D ICs enable dramatically improved performances at a much lower cost compared to new leading&#8211;edge CMOS technologies below 32 nm transistor fabrication&#046; The success of these new ICs highly depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity&#046; This workshop brings together key actors from semiconductor companies, system design houses and EDA industry to build a vision of the next step in 3D integrated ICs design&#046; Topics that will be addressed include: Applications requiring 3D, interconnect architectures and thermal management for 3D ICs, application partitioning, floorplanning for 3D architectures, modeling, characterization and testing of 3D ICs&#046;<br>