<p class="MsoPlainText">co–located with Int. Conf. on Field Programmable Logic and Applications (FPL)</p><p class="MsoPlainText"><br></p> <p class="MsoPlainText">*Scope of the Workshop*</p> <p class="MsoPlainText">The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high–level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken. However, to make this happen, there are still important issues to be solved that are in the focus of this workshop.</p> <p class="MsoPlainText"><br></p> <p class="MsoPlainText">*Topics of the FSP Workshop include, but are not limited to*<br></p><p class="MsoPlainText">o High–level synthesis and domain–specific languages (DSLs) for FPGAs and<span style="mso–spacerun:yes"> </span>heterogeneous systems</p><p class="MsoPlainText">o Mapping approaches and tools for heterogeneous FPGAs<br></p><p class="MsoPlainText">o Support of hard IP blocks such as embedded processors and memory interfaces<br></p><p class="MsoPlainText">o Development environments for software engineers (automated tool flows, design <span style="mso–spacerun:yes"></span>frameworks and tools, tool interaction)<br></p><p class="MsoPlainText">o FPGA virtualization (design for portability, hardware abstraction, etc.)<br></p><p class="MsoPlainText">o Design automation technologies for multi–FPGA and heterogeneous systems<br></p><p class="MsoPlainText">o Methods for leveraging (partial) dynamic reconfiguration to increase<span style="mso–spacerun:yes"> </span>performance, flexibility, reliability, or programmability<br></p><p class="MsoPlainText">o Operating system services for FPGA resource management, reliability, security<br></p><p class="MsoPlainText">o Target hardware design platforms (infrastructure, drivers, portable systems)</p> <p class="MsoPlainText">o Overlays (CGRAs, vector processors, ASIP– and GPU–like intermediate fabrics)</p> <p class="MsoPlainText">o Applications (embedded computing, signal processing, bio informatics,<span style="mso–spacerun:yes"> </span>big data, database acceleration, etc.) o Directions for collaborations (research proposals, networking, Horizon 2020)</p>
Abbrevation
FSP
City
Muenchen
Country
Germany
Deadline Paper
Start Date
End Date
Abstract