<p class="MsoNormal"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;color: rgb(68,68,68);">The 2015 technical program will consist of <a href="https://3c.gmx.net/mail/client/dereferrer?redirectUrl=http%3A%2F%2Fapp.content.ubmtechelectronics.com%2Fe%2Fer%3Fs%3D657486201%26lid%3D7782%26elq%3Dacd7463685db426e9572bb44ded60b21" target="_blank"><strong><span style="font–family: Verdana , sans–serif;">14 tracks</span></strong></a> covering: </span></p><ol start="1" type="1"><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Optimize Chip–Level Designs for Signal and Power Integrity </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Overcome Analog and Mixed–Signal Modeling and Simulation Challenges </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Wireless and Photonic Integration</span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">System Co–Design: Chip/Package/Board: Modeling and Simulation</span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Characterize PCB Materials and Processing Characterization </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Apply PCB Design Tools </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Design Parallel and Memory Interfaces </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Optimize High–Speed Serial Design </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Detect and Mitigate Jitter, Crosstalk, and Noise </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Leverage High–Speed Signal Processing for Equalization and Coding </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Ensure Power Integrity in Power Distribution Networks</span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Achieve Electromagnetic Compatibility and Mitigate Interference </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Apply Test and Measurement Methodology </span></li><li class="MsoNormal" style="color: rgb(68,68,68);margin–bottom: 3.75pt;"><span style="font–size: 10.5pt;font–family: Verdana , sans–serif;">Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques</span></li></ol>
City
Santa Clara
Country
United States
Deadline Paper
Start Date
End Date
Abstract