DVCon India solicits presentations that are highly technical and reflect real life experiences in using languages, standards, methods and Electronic Design Automation (EDA) tools.<br>In the DV Track we are soliciting detailed abstracts from industry leaders to share their ideas, thoughts and experiences in solving some of the most complex challenges in their respective fields of work/research. This track provides a platform for the wide Design–Verification community including beginners, architects/experts, managers and EDA vendors to share their knowledge, experiences and best practices about Design–Verification. Submissions are encouraged in (but not restricted to) the following topics:<br>– Using multiple HDLs and/or HVLs in a design cycle<br>– Novel application of existing standard DV (Design–Verification) languages such as SystemVerilog, PSL, e, VHDL, etc.<br>– Latest language developments in SystemVerilog<br>– Advanced stimulus generation methods, reuse of stimulus across levels of verification (portable stimulus)<br>– System–on–Chip Verification approaches to handle complexity, performance and reusability requirements<br>– Adoption of UVM<br>– Advanced techniques/features and extensions to UVM<br>– Real life applications of assertions using SVA and/or PSL<br>– Formal and semi–formal techniques, Assertion automation/synthesis<br>– Verification process and resource management<br>– Compliance and requirements–driven verification such as DO–254 standards<br>– Debug automation through transaction–level debug, smart tricks to handle performance issues, faster time to debug techniques<br>– Low Power intent verification through standards such as UPF and related technologies<br>– Usage of IPXACT and SystemRDL in design flow<br>– AMS challenges in Verification, usage of custom extensions to UVM/SystemVerilog to handle AMS related complexities<br>
Abbrevation
DVCon India
City
Bangalore
Country
India
Deadline Paper
Start Date
End Date
Abstract