Workshop on A Roadmap for EDA Research in the Dark Silicon Era, San Jose, Vereinigte Staaten

Link

http://ces.itec.kit.edu/EDA4DS/

City

San Jose

Country

United States

Deadline Paper

2014-09-05

Start Date

2014-11-06

End Date

2014-11-06

Abstract

Supply voltage scaling has slowed down in the leakage dominated nanometer era because a lower supply voltage necessitates a lower threshold voltage (for iso–performance), which in turn exponentially increases leakage power consumption. As a result, although we can integrate more transistors per unit area with technology scaling, the switching power per transistor does not scale commensurately. Coupled with the physical limits imposed by device packaging and cooling technology on the peak power and peak power density, this results in the so–called dark silicon problem, i.e., not all parts of the chip can be simultaneously powered on at nominal voltage. It is projected that at the 8 nm technology node, 50%–80% of the chip area will be dark. The dark silicon challenge is essentially one of determining how best to utilize the abundance of (potentially dark) transistors, both in terms of design time provisioning and run–time management, so as to improve quality metrics (performance, reliability, lifetime, etc.) within peak power and thermal constraints. The EDA community has potentially much to contribute here because dark silicon also opens up a vast design space of potential solutions: navigating this design space in a computationally efficient way to narrow down on the most promising solutions is, fundamentally, an EDA challenge. This workshop is intended to provide a common platform for EDA experts to discuss their vision and perspectives on the dark silicon problem, and to define a research roadmap for the next decade. This workshop will bring together researchers and experts from industry and academia to dwell on whether fundamentally new solutions are required in the context of dark silicon, or conversely, whether existing solutions can be retro–fitted to address these problems. In either scenario, a lively, but informative technical debate is envisioned that will help to carve out a distinct niche for dark silicon research. In keeping with its intent to encourage a diversity of opinions, this workshop will attempt to include speakers in the agenda with alternate perspectives (ÃƒÂ¢Ã¢â€šÂ¬Ã…â€œdark silicon is just old wine in a new bottle!ÃƒÂ¢Ã¢â€šÂ¬Ã‚Â). Topics of interest include, but are not limited to: Exploiting new architectural opportunities in next generation dark silicon chips including but not limited to heterogeneous, reconfigurable and application–specific design paradigms. Efficient and scalable run–time dark silicon management under power and thermal considerations while jointly optimizing for quality metrics including performance, reliability, lifetime, etc. Opportunities and challenges in gray silicon (e.g. using near–threshold voltage computing) including analysis, modeling, variability and reliability challenges. On–chip communication architectures for dark silicon chips, e.g., efficient data transfer mechanisms between different parts of the chip. Integration of new device (steep–slope devices, nano–electromechanical switches, etc.) and cooling technologies (e.g., phase change materials) and their interaction with dark silicon. Programming models, compiler and operating system support for dark silicon chips with specialized resources, adaptive modes of parallelism, etc. Killer application domains (mobile, big data, enterprise, etc.) for dark silicon: shrinking die size versus more (dark) transistors in the same area.