2nd International Workshop on the Design and Performance of Networks on Chip, Belfort, Frankreich

The advance in silicon technology has led to the emergence of on&#8211;Chip Systems (SoC), where a complete system with a large number of intellectual property cores can be integrated onto a single silicon chip&#046; The performance of SoCs highly depends on the speed and efficiency of their underlying communications subsystems&#046; The light weight networks, known as Network&#8211;on&#8211;Chip (NoC), have been introduced to overcome the scalability problem found in shared&#8211;bus communication architectures&#046; Intensive research studies have been undertaken investigating the design cost, in terms of silicon area and power consumption, and performance of NoC&#046; Most of these studies are targeting NoC topology, router microarchitecture, switching techniques, routing algorithms, and application mapping onto NoC&#046;<br>The workshop on the Design and Performance of Networks on Chip (DPNoC&#8242;2015) will represent an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in this area&#046; The Workshop topics include (but are not limited to) the following:<br>Router microarchitecture<br>Flow control techniques<br>Switching techniques<br>Routing protocols<br>Fault tolerance/reliability in NoC<br>Technology constraints on NoCs<br>Scheduling and application mapping onto NoC<br>Wireless NoCs<br>NOCs modeling and performance evaluation<br>NOC scalability<br>FPGA&#8211;based implementation of reconfigurable NoCs<br>