9 th IEEE /ACM International Symposium on Networks - on - Chip, VancouverB.C., Kanada

Abbrevation

NOCS

Link

http://school.eecs.wsu.edu/uploads/files/NOCS2015.pdf

City

VancouverB.C.

Country

Canada

Deadline Paper

2015-03-16

Start Date

2015-09-28

End Date

2015-09-30

Abstract

NoC ArchiteNOCS is the premier forum for researchers to present their latest findings in the area of Networks–on–Chip. The International Symposium on Networks–on–Chip (NOCS) is the premier event dedicated to interdisciplinary research on on–chip, chip–scale, and multichip package–scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter–related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, co–design, and design automation. Topics of interest include, but are not limited to: NoC Architecture and Design Network architecture (topology, routing, arbitration) NoC Quality of Service Timing, synchronous/asynchronous communication Network interface issues NoC design methodologies and tools Mapping of applications onto NoCs Signaling & circuit design for NoC links NoC Application NoC case studies application–specific NoC designs NoC designs for heterogeneous many–core systems, fused CPU–GPU architectures, FPGA–based systems etc NoC Analysis, Verification and Modeling NoC Analysis, Verification and Modeling Modeling, simulation, and synthesis of NoCs Verification, debug & test of NoCs Metrics and benchmarks for NoCs Scalable modeling of NoCs NoC at the Un–Core and System–level Design of memory subsystem (un–core) including memory controllers, caches, cache coherence protocols & NoCs NoC support for memory and cache access OS support for NoCs Programming models including shared memory, message passing and novel models Issues related to large–scale systems (datacenters, supercomputers) with NoC–based systems as building blocks Novel NoC Technologies New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through–silicon, etc. NoCs for 3D and 2.5D packages Package–specific NoC design Optical, RF, & emerging technologies for on–chip/in–package interconnects NoC Optimization for power/energy efficiency for thermal efficiency and darksilicon for dependable architectures for communication efficient algorithms