System Level Interconnect Prediction, San Francisco, Vereinigte Staaten

Abbrevation

SLIP

Link

http://www.sliponline.org/

City

San Francisco

Country

United States

Deadline Paper

2015-03-10

Start Date

2015-06-06

End Date

2015-06-06

Abstract

The general technical scope of the workshop is the design, analysis, predic6on, and op6miza6on of interconnect and communica6on fabrics in electronic systems. The organizing commi<ee invites original contribu6ons to the workshop. These contribu6ons include papers, tutorials, panels, special sessions, and posters. We accept papers based on novelty and contribu6ons to the advancement of the field. The accepted papers will be published in the ACM and IEEE digital libraries. Technical topics include but are not limited to: Interconnect predic6on and op6miza6on at various IC and system design stages System–Ââ€level design for FPGAs, NOCs, reconfigurable systems Design, analysis, and op6miza6on of power and clock networks Interconnect reliability Interconnect topologies and fabricechnical topics include but are not limited to: Interconnect predic6on and op6miza6on at various IC and system design stages System–Ââ€level design for FPGAs, NOCs, reconfigurable systems Design, analysis, and op6miza6on of power and clock networks Interconnect reliability Interconnect topologies Design–Ââ€for–Ââ€manufacturing (DFM) and yield techniques for interconnects High speed chip–Ââ€to–Ââ€chip interconnect design Design and analysis of chip–Ââ€package interfaces Power consump6on of interconnects 3D interconnect design and predic6on Emerging interconnect technologies Applica6ons of interconnects to social, gene6c, and biological systems Co–Ââ€op6miza6on of interconnect technology and chip