<p>The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design.</p> <p>The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or <span class="e">e</span>; assertions in SVA or PSL; the use of AMS languages; design automation using IP–XACT; and the use of general purpose languages C and C++.</p> <p>This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip–cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below. Low power techniques and design for functional safety (e.g., ISO 26262, DO–254) are pervasive and can be addressed in any of these topics areas.</p> <div class="twocol_one first"><strong>Topic area 1: System–level design</strong> <ul><li>Requirements–driven design including traceability</li><li>Virtual and hardware–assisted prototyping</li><li>Architecture exploration</li><li>Hardware/software/embedded co–design</li><li>System–on–chip and network–on–chip design</li><li>System development methodologies and flows</li><li>High–level synthesis from ESL languages</li><li>Safety and security in system–level design</li></ul> <p><strong>Topic area 3: IP reuse and design automation</strong></p> <ul><li>Interoperability of models and/or tools</li><li>IP tagging, protection or security</li><li>SoC and IP integration methods, flows, and tools</li><li>Configuration management of IPs including different abstraction levels</li><li>Flow and tool automation (e.g., IP–XACT)</li></ul> </div><strong>Topic area 2: Verification & Validation</strong> <ul><li>Requirements–driven verification including traceability</li><li>Verification process, reuse and resource management</li><li>Methods bridging between verification and validation</li><li>Hardware/software co–verification</li><li>Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs, testbench automation)</li><li>Testbench qualification</li><li>Formal and semi–formal techniques</li><li>Safety and security in verification and validation</li></ul> <p><strong>Topic area 4: Mixed–signal design and verification</strong></p> <ul><li>AMS concept and system design</li><li>Application of mixed–signal extensions (e.g., UVM)</li><li>Real–number modeling approaches</li><li>Mixed–signal design and verification techniques (applied on proper abstraction level)</li><li>Self–checking in analog verification</li></ul>
Abbrevation
DVCon Europe
City
Munich
Country
Germany
Deadline Paper
Start Date
End Date
Abstract