WCET workshop is the reference forum for academics, practitioners and industrials<br>in any aspect related to the timing analysis of computer systems. While in the past<br>timing analysis has been a topic mainly for real–time systems, recently it has<br>becoming crucial in other domains dealing with timing guarantees. This includes<br>among other mobile computing and high–performance computing. This edition of the<br>WCET workshop, besides papers targeting traditional WCET analysis, encourages<br>submissions focused on less rigorous and mature timing analysis techniques on complex<br>multicore and manycore heterogeneous, usually COTS, architectures. For such complex<br>architectures Execution Time Bound (ETB) estimates are derived rather than WCET<br>estimates in the strict sense. ETB estimates are intrinsically less reliable<br>than WCET estimates.<br>TOPICS<br>This workshop seeks original contributions on topics that include but<br>are not limited to:<br>– WCET/ETB analysis for multi– and many–core systems<br>– WCET/ETB analysis for multi–threaded applications<br>– WCET/ETB analysis for COTS processors<br>– Case studies, and industrial experience of WCET/ETB analysis<br>– Timing Analysis and safety standards<br>– Different approaches to WCET/ETB computation<br>– Probabilistic timing analysis<br>– Tools for WCET/ETB analysis<br>– Timing–predictable operating systems and processor designs<br>– Compiler–based optimization of worst–case timing<br>– Low–level timing analysis, modelling and analysis of processor features<br>– Flow analysis for WCET, loop bounds, infeasible paths<br>– Integration of timing analysis and schedulability analysis<br>– Integration of timing analysis in development processes<br>– Methods and benchmarks for timing analysis evaluation<br>
Abbrevation
WCET
City
Lund
Country
Sweden
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