Design and Verification Conference & Exhibition India, Bangalore, Indien

Abbrevation

DVCon India

Link

http://dvcon-india.org/conf/call-for-abstracts/

City

Bangalore

Country

India

Deadline Paper

2015-06-30

Start Date

2015-09-10

End Date

2015-09-11

Abstract

The Design and Verification Conference & Exhibition India (DVCon India) is a highly technical conference in India targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems, embedded systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India is similar to the successful DVCon United States conference held for over 10 years in the Silicon Valley. The ultimate goal of DVCon India is to boost the interest, usage and development of electronic system designs. We look forward to users sharing the various challenges and solutions adopted by various teams across the industry. DVCon India also provides a much–needed platform to promote upcoming Electronic Design Automation (EDA) and Intellectual Property (IP) standards in India. This highly technical 2–day conference is organized to invite industry experts to learn and share best practices on: Modeling, Design and Verification of complex electronic systems at different levels of abstraction such as Virtual prototyping, Architectural Modeling, RTL, Emulation, HW acceleration, etc. The application of system–level design and verification languages such as SystemC and SystemVerilog Virtual Platform for Embedded Software Development Novel application of standard Design & Verification languages such as SystemVerilog, PSL, e, VHDL, etc. SoC Design Verification using the latest trends and methodologies such as UVM–SystemC, graph–based techniques, portable stimulus across block–subsystem–system all the way up to Post–Silicon Architectural Exploration at the early stage and High–level Synthesis The use of SystemVerilog Assertions (SVA), PSL and Formal Verification (Model Checking) Adoption of Universal Verification Methodology (UVM) Leveraging on legacy methodologies based on OVM, VMM and migration to UVM IP reuse, design automation and integration standards based on IP–XACT and SystemRDL Low–power design and verification using the Unified Power Format (UPF) General topic areas on Electronic System Level (ESL), Virtual Platform, Verification & Validation, Analog/Mixed–Signal, IP reuse, Design Automation, and Low–power design and verification will be highlighted in tutorials, papers, and poster sessions.