The Program Committee cordially invites you to participate and submit your contribution to DFT 2015. The conference topics include (but are not limited to) the following:<br>Yield Analysis and Modeling<br>Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.<br>Testing Techniques<br>Built–in self–test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.<br>Design For Testability in IC Design<br>FPGA, SoC, NoC, ASIC, microprocessors.<br>Error Detection, Correction, and Recove– ry<br>Self–testing and self–checking solutions; error–control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.<br>Dependability Analysis and Validation<br>Fault injection techniques and environments; dependability characterization.<br>Repair, Restructuring and Reconfiguration<br>Repairable logic; reconfigurable circuit design; DFT for on–line operation; self–healing.<br>Defect and Fault Tolerance<br>Reliable circuit/system synthesis; radiation hardened/tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors.<br>Totally Fail–Safe Design for Critical Applications<br>Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.<br>Emerging Technologies<br>DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self–assembly.<br>Hardware security<br>Fault attacks, fault tolerance–based counter– measures, Scan–based attacks and countermeasures, hardware trojans, security vs reliability trade–offs, interaction between VLSI test, trust, and reliability.<br>
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DFT
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City
Amherst
Country
United States
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