<p>A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed–signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices.<strong> All past Conference proceedings & Papers have been published in IEEE Xplore digital library and indexed by Scopus.</strong></p> <ol><li>Electronic Design <ol><li>System–level Design, Methodologies & Tools</li><li>IOT & Smart Sensors – Technology and Design </li><li>FPGA Architecture, Design, and CAD</li><li>IC Package – Design Interactions & Co–Design</li><li>Advanced 3D ICs & 3D Packaging</li><li>Robust & Power–conscious Circuits & Systems</li><li>Emerging/Innovative Process & Device Technologies and Design Issues</li><li>Design of Reliable Circuits and Systems</li><li>Design of Embedded Systems</li></ol> </li><li>Design Automation and IP <ol><li>IP Design, quality, interoperability and reuse</li><li>Design Verification and Design for Testability</li><li>Physical Design, Methodologies & Tools</li><li>EDA Methodologies, Tools, Flows</li></ol> </li><li>Manufacturing, Semiconductor Process and Devices <ol><li>Design for Manufacturability/Yield & Quality</li><li>Effects of Technology on IC Design, Performance, Reliability, and Yield</li></ol> </li><li>Hardware and System Security</li><li>Cognitive Computing in Hardware (NEW in ISQED 2016)</li></ol> <p>The details of various topics of paper submission is as follows:</p> <h3><a name="isqed_topics"></a>Cognitive Computing in Hardware (CCH) </h3> <p>Hardware accelerators for machine learning and deep learning algorithms including Support Vector Machines, Neural Networks, Hidden Markov Model Decoding, and Genetic Algorithms. Machine learning algorithms optimized for CPUs or general purpose GPUs (GPGPUs). FPGA–accelerated implementations of machine learning algorithms. Hardware implementations of machine learning algorithms for applications like image/object recognition, computer vision, speech recognition, and natural language processing. Machine–learning based intelligence in IoT under highly constrained energy/power requirements. System–wide partitioning for deep learning algorithms: algorithm training and recognition from cloud/server to IoT node.</p> <h3>Hardware and System Security (HSS)</h3> <p>Hardware security attacks including (but not limited to) side–channel attacks, reverse engineering, tampering, and Trojans. Supply–chain integrity. Security for memory technologies. Hardware–based security primitives including PUFs, TRNGs, and ciphers. Design of encryption circuits. Security, privacy, trust protocols, and trusted information flow using hardware security primitives. Trusted design automation using untrusted tools. Trusted manufacturing including split manufacturing, remote IC enabling/disabling, watermarking, and fingerprinting. Techniques and metrics for hardware/software usage metering; evaluating system–data/hardware–design confidentiality, integrity, and authenticity; and, ensuring system security.</p> <h3>Design Technology Co–Optimization (DTCO)</h3> <p>Optimization–based methodologies that address the interaction between design (custom, semi–custom, ASIC, FPGA, RF, memory, etc.) and advanced node manufacturing techniques such as multiple patterning, EUV lithography, DSA lithography, and advanced interconnect (e.g., air gap for local interconnect, Si photonics, etc.). Modeling, analysis, and optimization of technology implications on performance metrics like power consumption, timing, area, and cost. Design methods and tools to improve yield and manufacturability.</p> <h3>Design Verification and Design for Testability (DVFT)</h3> <p>Hardware and software formal–, assertion–, and simulation–based design verification techniques to ensure the functional correctness of hardware early in the design cycle. DFT and BIST for digital designs, analog/mixed–signal IC′s, SoC′s, and memories. Test synthesis and synthesis for testability. DFT economics, DFT case studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction. SoC/IP testing strategies. Design methodologies dealing with the link between testability and manufacturing.</p> <h3>EDA, Physical Design, and IP Cores (EDA)</h3> <p>EDA and physical design tools, processes, methodologies, and flows that address issues such as: large–scale SoC design, low–power design, noise sensitivity reduction, reliable clock distribution, timing closure, parasitic extraction, and reliable power grid design and analysis. Design tools for analysis/ tolerance of variation, aging, and soft–errors. Design and maintenance of hard and soft IP blocks, including methods and tools for analysis, comparison, and qualification of IP blocks. Challenges and solutions of integrating, testing, qualifying and manufacturing IP blocks from multiple vendors. Application of EDA to non–traditional problems such as smart power grid, Solar energy, etc.</p> <h3>Emerging Process & Device Technologies and Design Issues (EDT)</h3> <p>Emerging processes and device technologies and implications on IC design. Emerging technologies including tunnel FETs, steep switching slope devices, horizontal/vertical nanowires, carbon nanotubes, and other nano–devices. Device design and circuit optimization in emerging non–volatile memory and logic, such as Spin–Transfer Torque RAM, Phase Change Memory, Resistive RAM, and Memristors. Use of emerging devices for cognitive, neuromorphic, or quantum computing. Specialty technologies such as MEMs, CIS co–integration with application processors for the IoT market.</p> <h3>Integrated Circuit Design (ICD)</h3> <p>Low power, high–performance, and robust design of logic, memory, analog, RF, programmable logic, and FPGA circuits. Techniques for leakage control, power optimization, and power management including integrated voltage regulators. Clock–generation and distribution circuits, including all–digital PLLs and DLLs. Low power on–chip and chip–to–chip interconnect solutions. Analog– to–digital and digital–to–analog converters. Adaptive digital circuits and systems. Soft–error and fault–tolerant circuits. Circuit design for reliability effects such as gate oxide integrity, electromigration, ESD, HCI, NBTI, PBTI etc. On–chip process, voltage, temperature, and aging sensors and monitoring.</p> <h3>Smart Sensors for IoT – Design and Technology (SSDT)</h3> <p>Sensor and actuator devices for use in IoT applications like Smart Home/Office automation, robotics, connected vehicles, aircraft, wearable systems, implantable electronics, environmental monitoring, and other industrial uses. Device technologies for sensors including MEMS, magnetic, optical, chemical, and biological. Hardware design for sensors including interface, calibration, energy harvesting, signal processing, and power management. Software design for smart sensors including data processing algorithms and information fusion. Sensor network design and processing.</p> <h3>System–level Design and Methodologies (SDM)</h3> <p>Emerging system–level design paradigms, methods and tools aiming at quality of systems including multi–core processors, graphics processors; embedded systems, SoC, novel accelerator designs, and heterogeneous architecture designs. System–level trade–off analysis and multi–objective (e.g. yield, power, delay, area, etc.) optimization. System level power and thermal management. The influence of nanometer technology issues on the system level design. System level modeling and simulation to characterize effects of process, voltage, temperature, and aging on power, performance, and reliability.</p> <h3>Three Dimensional Integration and Advanced Packaging (TDIP)</h3> <p>Innovative packaging technologies including 3D IC, 2.5D or interposer, and multi–chip module and their impact on system design. Design techniques, methodologies, flows and EDA solutions for vertically integrated circuits/chips such as 2.5D, TSV–based 3D, and monolithic 3D design including novel partitioning, power delivery design, clock tree design, reliable high–frequency signal communication, heatsink/cooling methods, and design–for– yield techniques. Modeling and mitigation of via–to–via and via–to–device interactions for 3D ICs. Design of die–to–die interfaces in 3D/2.5D ICs. Design–for–testability for 3D/2.5D ICs. System–level design issues in 3D/2.5D. Die–package co–design.</p><p><br></p>
Abbrevation
ISQED
City
Santa Clara, CA
Country
Germany
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Abstract