Authors are invited to submit papers on any aspect of synchronous design topics ranging from design, synthesis, and test, to asynchronous applications in system–level integration and emerging computing technologies. Topics of interest include:<br>Mixed–timed circuits, GALS systems, Networks–on–Chip, and multi–chip interconnects;<br>Elastic and latency–tolerant synchronous design;<br>Asynchronous pipelines, architectures, CPUs, and memories;<br>Asynchronous ultra–low power systems, energy harvesting, and mixed–signal/analogue;<br>Asynchronous logic in power–constrained applications;<br>Asynchronous techniques for 3D integration;<br>Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing;<br>CAD tools for asynchronous design, synthesis, analysis, and optimization;<br>Formal methods for verification and performance/power analysis;<br>Test, security, and fault tolerance;<br>Asynchronous variability–tolerant design and design for manufacturing;<br>Circuit designs, case studies, comparisons, and applications.<br>
Abbrevation
ASYNC
City
Porto Alegre
Country
Brazil
Deadline Paper
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Abstract