Regular Papers<br>Authors are invited to submit papers on any aspect of synchronous design topics ranging from design, synthesis, and test, to asynchronous applications in system–level integration and emerging computing technologies. Topics of interest include:<br>Mixed–timed circuits, GALS systems, networks–on–chips, multi–chip interconnects, and 3D integration;<br>Elastic and latency–tolerant synchronous design;<br>Asynchronous pipelines, architectures, CPUs, and memories;<br>Asynchronous logic in ultra–low power and power–constrained systems, energy harvesting and mixed–signal/analog design;<br>Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing;<br>CAD tools for asynchronous design, synthesis, analysis, and optimization;<br>Formal methods for verification and performance/power analysis;<br>Test, security, fault tolerance, and radiation–hard design;<br>Asynchronous variability–tolerant, resilient design and design for manufacturing;<br>Asynchronous design for neural networks and machine learning applications;<br>Circuit designs, case studies, comparisons, and application<br>Industrial Papers<br>ASYNC 2017 will include a special industrial workshop with papers and tutorials from industry on the state–of–the–art application of asynchronous designs to both existing and emerging technologies. The topics are specifically targeted at industry and include:<br>Synchronizers and clock domain crossing techniques;<br>Techniques for combining asynchronous and clocked designs;<br>CAD tools for integrating asynchronous circuits with clocked designs;<br>Circuit designs, case studies, comparisons, and applications.<br>
Abbrevation
ASYNC
City
San Diego
Country
United States
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