Workshop on HPC Computing in a Post Moore's Law World, Frankfurt, Deutschland

Abbrevation

HCPM

Link

http://workshops.postmoore.org/hcpn2017/

City

Frankfurt

Country

Germany

Deadline Paper

2017-03-06

Start Date

2017-06-22

End Date

2017-06-22

Abstract

HPCM aims to discuss potential strategies, opportunities, and challenges for supercomputing beyond the scaling limits of Moore’s Law. Due to the multidisciplinary nature of this problem, formulating a strategy is likely to require a comprehensive re–thinking of technologies, ranging from innovative materials and devices, circuits, system architectures, programming systems, system software, and applications. HPCM will feature paper presentations, keynote addresses, and short panels to foster foster interdisciplinary dialog across the necessary spectrum of stakeholders: applications, algorithms, software, and hardware, from academia and industry alike. Many important questions need to be addressed, such as what technologies are the most promising candidates for the future, the impact to the software layer such as applications, algorithms compilers and programming models, impact to the architectures such as interconnects, parallelism, and the memory hierarchy, as well as challenges in modeling and simulation of future architectures. However, this list is by no means an exhaustive list of questions. This list is not exhaustive. Any topic relevant to the future of HPC as tied to the future of Moore′s law is relevant. – Optics and photonics, to include communication, switching, and other emerging topics. – Neuromorphic computing. Its current state, as well as future trends for performance and applicable application domains. – Quantum computing. Manufacturability, feasibility, application domains, as well as current implementations. – Superconducting circuits. – Novel device technologies that conform to the digital computing model, such as tunnel FETs, negative capacitance FETs, and carbon nanotube FETs. – Novel memory technologies such as resistive RAM, magnetic RAM and other volatile and nonvolatile options. – 3D integration. Future capabilities in terms of number of layers, types of layers (memory versus logic), as well as challenges such as heat density. – Impact of new technologies to the architecture, to include interconnect, memory hierarchy (such as caches), parallelism, ISA choice, etc. – Inexact computing such as approximate computing. What kinds of applications can tolerate errors, and how to use this strategy to mitigate technology problems. – Identifying the main application drivers for increased performance. – Modeling and evaluation of novel technologies. – Software impact of novel technologies, to include programmability, application algorithms, compilation, run–time systems, and other topics. – Funding opportunities for research in this field.