<br>DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state–of–the–art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.<br>Topics<br>Yield Analysis and Modeling<br>Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.<br>Testing Techniques<br>Built–in self–test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.<br>Design For Testability in IC Design<br>FPGA, SoC, NoC, ASIC, low power design and microprocessors.<br>Error Detection, Correction, and Recovery<br>Self–testing and self–checking design; error–control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural–specific techniques; system–level design–time or runtime strategies.<br>Dependability Analysis and Validation<br>Fault injection techniques and frameworks; system′s dependability and vulnerability characterization.<br>Repair, Restructuring and Reconfiguration<br>Repairable logic; reconfigurable circuit design; DFT for on–line operation; self–healing; reliable FPGA–based systems.<br>Design for Defect and Fault Tolerance<br>Reliable circuit/system synthesis; radiation hardened/tolerant processes and design; design space exploration for dependable systems; transient/soft faults and errors.<br>Aging and Lifetime Reliability<br>Aging characterization and modeling; design and run–time reliability, thermal, and variability management and recovery.<br>Dependable Applications and Case Studies<br>Methodologies and case study applications to Internet of Things, automotive, railway, avionics and space, autonomous systems, industrial control, etc.<br>Emerging Technologies<br>Techniques for 3D stacked ICs, quantum computing architectures, microfluid biochips, etc.<br>Design for Security<br>Fault attacks; fault tolerance–based countermeasures; hw security assurance, hw trojans, resistance to persistent DoS, security vs. reliability trade–offs, interaction between VLSI test, trust, and reliability.<br>
Abbrevation
DFT
City
Cambridge
Country
UK
Deadline Paper
Start Date
End Date
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