Design & Verification Conference & Exhibition, San Jose, Vereinigte Staaten

Abbrevation

DVCon

Link

https://dvcon.org/call-extended-abstracts

City

San Jose

Country

United States

Deadline Paper

2017-09-08

Start Date

2018-02-26

End Date

2018-03-01

Abstract

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading–edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. In addition to the specific topic areas suggested below, submissions may incorporate: usage of Electronic Design Automation (EDA) tools such as simulation, emulation, formal verification, virtual prototyping and/or FPGA prototyping FPGA–based designs usage of specialized design and verification languages such as SystemVerilog, SystemC, and e assertions in SVA or PSL the use of general purpose and scripting languages such as C, C++, Perl, Python, Tcl and others applications of the new Accellera Portable Stimulus Standard applications of design patterns or other innovative language techniques the use of AMS languages Internet of Things applications Topic Area 1: Verification & Validation Advanced methodologies and testbenches Verification processes, regressions and resource management Debug and analysis of complex designs Multi–language design and verification Hardware/Software co–design and co–verification of embedded systems Topic Area 2: Safety–Critical Design and Verification Verification and DO–254 compliance Automotive ISO 26262 Design and Verification Challenges Medical or Industrial Verification Challenges Requirements–Driven Verification Methodologies IP protection and security Topic Area 3: Machine Learning and Big Data Automating the Optimization of Verification Processes Coverage metrics and data analysis Performance modeling and/or analysis Topic Area 4: Design and Verification Reuse and Automation Bridging verification and validation across multiple engines SoC and IP integration methods and tools Automated stimulus generation methods Configuration management of IP and abstraction levels Interoperability of models and/or tools High–level synthesis from ESL languages Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping Topic Area 5: Mixed–Signal Design & Verification Mixed–signal design & verification techniques Real–value modeling approaches Application of mixed–signal extensions for UVM Topic Area 6: Low–Power Design & Verification Low–power design and verification Clock domain crossing verification Power modeling, estimation and management