VLSI–SoC 2018 is the 26th in a series of international conferences sponsored<br>by the International Federation for Information Processing Technical<br>Committee 10 Working Group 5, IEEE CEDA and IEEE CASS, which explore<br>the state–of–the–art in the areas of Very Large Scale Integration (VLSI) and<br>System–on–Chip (SoC) design. The purpose of VLSI–SoC is to provide a<br>forum to exchange ideas and showcase academic as well as industrial<br>research in architectures, circuits, devices, design automation, verifica–<br>tion, test, and security, within digital, analog, and mixed–signal systems.<br>VLSI–SoC 2018 will be held under the theme “Design and engineering of<br>electronics systems based on new computing paradigms” by addressing<br>cutting–edge research fields like heterogeneous, neuromorphic and<br>brain–inspired, biologically–inspired, approximate computing systems.<br>VLSI–SoC 2018 will be held in Verona, Italy. Verona, which has been<br>awarded World Heritage Site status by UNESCO because of its urban<br>structure and architecture, is the set of the Shakespeare’s Romeo and<br>Juliet play, one of the most visited Roman empire cities in northern Italy,<br>the capitol of the opera lyrics with its Arena roman amphitheater, the<br>land of the Amarone della Valpolicella vineyards.<br>Topics of interest include, but are not limited to:<br>– Analog, mixed–signal, and sensor architectures<br>– Digital architectures: NoC, multi– and many–core, hybrid, and reconfigurable<br>– CAD: Synthesis and analysis<br>– Prototyping, verification, modeling, and simulation<br>– Circuits and systems for signal processing and communications<br>– IoT, Embedded and Cyberphysical Systems: Architecture, design, and software<br>– Low–power and thermal–aware IC design<br>– Emerging devices and semiconductor technologies.<br>– Variability, reliability, and test<br>– Hardware security<br>– Machine learning for SoC design and for electronic design automation<br>
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VLSI-SoC
City
Verona
Country
Italy
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