The AISTECS workshop promotes research and knowledge exchange on evolutionary as well as revolutionary interconnect technologies, in the perspective of interconnects adoption at all scales: from high–performance computing systems and datacenters down to embedded devices and the Internet of Things.<br>Interconnects are subject to growing expectations in terms of performance and Quality of Service while being tied to shrinking power and cost budget, as well as thermal envelopes. To this end, the exploration of emerging interconnect technologies along with the design of disruptive/novel ideas at the microarchitectural network level are necessary. Both approaches lead to crucial challenges and interesting design tradeoffs that must be identified to enable widespread adoption of emerging technologies in next–generation computing platforms. Novel interconnect features may also disrupt the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives.<br>The AISTECS workshop aims to foster development of advanced interconnect solutions, for emerging computing systems, and using emerging technologies. To this aims, the workshop gathers a complete range of perspectives, spanning from raw technology issues and solutions up to studies at the overall system level of modern multi–/many–core systems. This encompasses novel network solutions from both academic and industrial researchers.<br>TOPICS OF INTEREST<br>– Communication infrastructures for HPC systems, Supercomputers and Data Centers<br>– Near range interconnects<br>– Networks on Chip (NoCs)<br>– Memory interconnect and coherence support<br>– Network architectures (topology, control–flow, routing, etc.)<br>– Integrated photonics based interconnects<br>– Silicon Interposer solutions and embedded multi–die interconnects<br>– Interconnect solutions for heterogeneous GPU/FPGA–based multi/macro–chip systems<br>– Emerging interconnect technologies (EIT): photonics, carbon nanotubes, through–silicon, RF, wireless NoC<br>– Crucial challenges and design tradeoffs for EIT in future computer systems<br>– Low–level technological improvements and implications of EIT in future communication systems<br>– Impact of the interconnect on application performance, and evaluation thereof<br>– Thermal–/energy–and power–related NoC optimization and dark silicon<br>– Reconfigurable/programmable interconnect components<br>– 2.5D and 3D packaging concerns for interconnects<br>– Asynchronous interconnect designs<br>– Clockless interconnects with focus on automation of their design methodology<br>– Network infrastructures for Internet–of–Things devices<br>– Network solutions for performance isolation in many–core systems<br>– Reliability, availability, fault tolerance for system communication<br>– Programming models for communication–centric systems<br>– Secure interconnection networks for intra–chip and inter–chip communication<br>
Abbrevation
AISTECS
City
Manchester
Country
UK
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End Date
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