The general technical scope of the workshop is the design, analysis, prediction, and optimization of interconnect and communication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, special sessions, and posters. We accept papers based on novelty and contributions to the advancement of the field. The accepted papers will be published in the ACM and IEEE digital libraries.<br>Technical topics include but are not limited to:<br>–Interconnect prediction and optimization at various IC and system design stages<br>– System–level design for FPGAs, NoCs, reconfigurable systems<br>– Design, analysis, and optimization of power and clock networks<br>– Interconnect reliability Interconnect topologies and fabrics of multi– and many–core architectures<br>– Design–for–manufacturing (DFM) and yield techniques for interconnects<br>– High speed chip–to–chip interconnect design<br>– Design and analysis of chip–package interfaces<br>– Power consumption of interconnects<br>– 3D interconnect design and prediction<br>– Applications of interconnects to social, genetic, and biological systems<br>– Co–optimization of interconnect technology and chip design<br>– Emerging interconnect technologies in machine learning platforms & chips<br>
Abbrevation
SLIP
City
San Francisco
Country
United States
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