Abbrevation
CASES
City
New York
Country
United States
Deadline Paper
Start Date
End Date
Abstract

&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;<br>Topics of Interests / Tracks<br>&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;<br>Compilers for Embedded Systems:<br>Compilation for power and performance; Compiler support for CPU, GPU,<br>reconfigurable computing, heterogeneous multi&#8211;core SoC; Compilation for<br>memory, storage, and on&#8211;chip communications&#046;<br>Processor Architectures:<br>Embedded and mobile processor micro&#8211;architecture, Multi&#8211; and many&#8211;core<br>processors, GPU architectures, Reconfigurable computing including FPGAs<br>and CGRAs, Application&#8211;Specific processor design, 3D&#8211;stacked<br>architectures; Power&#8211; and energy&#8211;efficient architectures&#046;<br>Memory and Storage:<br>Memory system architecture; Non&#8211;volatile and other emerging memory<br>technologies; Scratchpad memory, caches and compiler&#8211;controlled memories;<br>storage organization including flash storage&#046;<br>On&#8211;chip communication and I/O:<br>Networks&#8211;on&#8211;chip architectures and design methodologies; on&#8211;chip<br>communication synthesis, analysis, and optimization; I/O management<br>in embedded systems&#046;<br>Accelerators:<br>Synthesis, optimization, and Design&#8211;space exploration of high&#8211;<br>performance, low&#8211;power accelerators; Novel design paradigms for<br>accelerators including approximate computing and big&#8211;data analytics&#046;<br>Security, Reliability, and Predictability:<br>Secure architectures, hardware security, and compilation for software<br>security; Architecture and compiler techniques for reliability and aging;<br>Modeling, design, analysis, and optimization for timing and<br>predictability; Validation, verification, testing &amp; debugging of embedded<br>software&#046;<br>Emerging Applications:<br>Architectures and accelerators for machine learning, neuromorphic &amp;<br>cognitive computing, data analytics; biologically inspired computing<br>systems&#046;<br>Special Day on the Internet of Medical Things:<br>A special day will be jointly organized by the conferences in ESWEEK&#046;<br>Articles aligned to the topics of interest for CASES, with distinct<br>focus on medical devices/ healthcare platforms are welcome&#046;<br>