32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Delft, Niederlande

Abbrevation

DFT

Link

http://www.dfts.org/

City

Delft

Country

Netherlands

Deadline Paper

2019-05-17

Start Date

2019-10-02

End Date

2019-10-04

Abstract

The symposium is going to Europe for its 32nd edition and will be co–hosted by the Space Research and Technology Centre of the European Space Agency (ESA–ESTEC) and TU Delft, Netherlands. The first two days of the symposium will be held at ESA–ESTEC and the 3 rd day will be held at TU Delft. The city of Leiden – which is between the two sites – is conveniently located close to Amsterdam International Airport and is connected by excellent rail and bus services to both sites. === ABOUT DFT === DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state–of–the–art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. === PROGRAM TOPICS === The topics include (but are not limited to) the following ones: 1. YIELD ANALYSIS AND MODELING Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics. 2. TESTING TECHNIQUES Built–in self–test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity. 3. DESIGN FOR TESTABILITY IN IC DESIGN FPGA, SoC, NoC, ASIC, low power design and microprocessors. 4. ERROR DETECTION, CORRECTION, AND RECOVERY Self–testing and self–checking solutions; error–control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system–level techniques. 5. DEPENDABILITY ANALYSIS AND VALIDATION Fault injection techniques and frameworks; dependability and characterization. 6. REPAIR, RESTRUCTURING AND RECONFIGURATION Repairable logic; reconfigurable circuit design; DFT for on–line operation; self– healing; reliable FPGA–based systems. 7. DEFECT AND FAULT TOLERANCE Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults. 8. RADIATION EFFECTS SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques. 9. AGING AND LIFETIME RELIABILITY Aging characterization and modeling; design and run–time reliability, thermal, and variability management and recovery. 10.DEPENDABLE APPLICATIONS AND CASE STUDIES Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc. 11.EMERGING TECHNOLOGIES Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc. 12.DESIGN FOR SECURITY Fault attacks, fault tolerance–based countermeasures, scan–based attacks and countermeasures, hardware trojans, security vs. reliability trade–offs, interaction between VLSI test, trust, and reliability.