The 33rd International Conference on VLSI Design & The 19th International Conference on Embedded Design, Namma Bengaluru, Indien

Abbrevation

VLSID

Link

http://embeddedandvlsidesignconference.org/

City

Namma Bengaluru

Country

India

Deadline Paper

2019-06-16

Start Date

2020-01-04

End Date

2020-01-08

Abstract

VLSI Design Conference started as a simple idea in 1985: to sense the level of VLSI activities in India with a focus on engineering education & research. Over the years, the conference has grown equilaterally with a VLSI community that includes the likes of Multinational Industries, Academic contributors and Government bodies around the globe. With its global footprints VLSID is recognized as a ′Sister Conference′ of Design Automation Conference. This conference is sponsored by VLSI Society of India (VSI). Topics Call For Papers Intelligent System Design  Embedded Systems Design: ESL, System–level design methodology, Processor and memory design, Concurrent interconnect, Networks–on–chip, Defect Tolerant Architectures, Hardware/Software Co–Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems,Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems–on–chip  Artificial Intelligence: Deep Neural Network, CNN, Computer Vision, On chip Neural Processing Engines, ML Algorithms  System Level Algorithms and Architectures: Platform Architectures, Chip Partitioning, Power Management, Board Level Design, Packaging, Signal Integrity, Power/Thermal Trade Off  High Performance Computing: Server Processor Architecture, Compute Efciency, Benchmark Enhancement, Edge Computing, Cloud Computing, Distributed Architecture, Heterogeneous Compute  Efficient Connectivity: Ethernet, Networking Algorithms, 5G, Communication Standards, LTE, Switching  Security: Security Protocols HW Security Design, SW Security, Architectures, Algorithms Efficient Component Design  Digital Design: Logic and Physical synthesis, Place & Route, Clock Tree Synthesis, Physical Verification, Static/Dynamic Timing, Signal integrity, xOCV, DFM/DFY, Physical Design for Debug  Analog Design: Analog Mixed Signal IP, High–Speed Interfaces, Various RAM design, IO Buffer,PLL/DLL Design, Standard Cell Design  FPGA: FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping  Power/Energy Efficiency: Digital/Analog Power Optimization Techniques, Power Architectures, Power/Performance Trade Off, Power Delivery Network, Power Switch, Power/Thermal Balance  Verification and Test: Verification and Test: Design for Test (DFT), Product Level Test, Design Verification Techniques, Mixed Signal Verification, Fault Tolerance, DPPM Betterment, Formal Verification, Emulation  Power Management and RF: Regulator Design, On Chip Regulator, RF Circuits, Effective Spectrum Utilization, New Transceiver Design in 5G Era, RF Certification, LDO Design, SMPS Design  Electronic Design Automation: Simulation Tools for Design Verification, SPICE Simulation,Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations  Emerging Technologies: Nano–CMOS Technologies, MEMS, CMOS Sensors, CAD/EDA Methodologies for Nanotechnology, Nano–Electronics and NanoCircuits, Nano–Sensors, MEMS Applications, Nano–Assemblies and Devices, NonClassical CMOS; Post–CMOS Devices; Biomedical Circuits, Carbon Nano–Tubes Based Computing New Age Transistors and Tools/Flows/Methodology  Electronic Design Automation: Simulation Tools for Design Verification, SPICE Simulation, Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations, Transistor Level Tools, EDA on Cloud  Transistor Level Design: Silicon Technology Advancements, FinFET, Beyond FinFET, Transistor Level Performance Improvements, Device Microelectronics, Beyond Silicon, PVT Optimization, Design Optimization Corners, Yield Improvement, Post Tapeout Methodology