21st IEEE Latin American Test Symposium, Jatiúca (Maceió), Brazil,

The IEEE Latin–American Test Symposium (LATS) is a recognized test and fault tolerance techniques forum attended by professionals from all over the world, in particular from Latin–America, to present and discuss various aspects of system, board, and component testing as well as design, manufacturing and in–field considerations with fault tolerance in mind. All presented papers are published in the IEEE Xplore Digital Library and the best papers of its 21st edition will be invited to re–submit to IEEE Design&Test, Journal of Electronic Testing: Theory and Applications (JETTA – Springer), Journal of Low Power Electronics (JOLPE – American Scientific Publishers), and IEEE Transactions on Computer–Aided Design of Integrated Circuits and Systems (TCAD). Topics of interest include but are not limited to: – Automatic Test Generation – Built–In Self–Test – Defect–Based Test – Design and Synthesis for Testability – Design for Electromagnetic Compatibility – Design for Reliable Embedded Software – Design Verification / Validation – Economics of Test – Fault Analysis and Diagnosis – Fault Modeling and Simulation – Fault–Tolerance in HW/SW – Fault–Tolerant Architectures – Memory Test and Repair – On–Line Testing – Process Control & Measurements – Radiation / Electromagnetic Interference – Hardening Techniques – Software Fault–Tolerance – Software On–Line Testing – System–on–Chip Test – Test Resource Partitioning – Yield Optimization – Hardware Security