Design and Verification Conference & Exhibition Europe, Munich, Deutschland

Abbrevation

DVCon Europe

Link

https://dvcon-europe.org/

City

Munich

Country

Germany

Deadline Paper

2019-04-18

Start Date

2019-10-29

End Date

2019-10-30

Abstract

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design. The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP–XACT; and the use of general purpose languages C and C++. This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip–cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below. Topic Area 1: System–level design and verification Requirements–driven design and verification including traceability Architecture exploration Virtual and hardware–assisted prototyping Hardware/firmware/software/embedded co–design and verification System–on–chip and network–on–chip design High–level synthesis from ESL languages Interoperability of system models and/or tools Configuration management of system IPs, including different abstraction levels System development methodologies, flows and tool automation (e.g., IP–XACT) Topic Area 2: Design, verification and validation Requirements–driven design and verification including traceability Verification process, reuse and resource management Methods bridging between verification and validation Testbench qualification Formal and semi–formal techniques Interoperability of models and/or tools IP tagging, protection or security SoC and IP integration methods, flows, and tools Topic Area 3: Mixed–signal design and verification AMS concept and system–level design Application of mixed–signal extensions for verification (e.g., UVM–MS) Abstract modeling approaches (e.g., real number modeling, signal flow, etc.) Mixed–signal design and verification techniques (applied on proper abstraction level) Self–checking testbenches for analog verification Analog assertions Parametric verification, automation and regression for AMS designs Topic Area 4: Functional safety and security Functional safety and security in system–level design Functional Safety and security in design, verification and validation Design processes and flows for ISO26262, ASIL, DO–254, etc.